The invention relates to a circuit arrangement which includes
a first differential amplifier stage with two amplifier members whose main current paths PA1 at least one further differential amplifier stage, each of which includes two further amplifier members whose main current paths on the one hand are coupled to one another and, via a respective further reference current source, to the first reference potential and whose control terminals can be supplied with (a) further control signal(s). PA1 the output impedances are preferably constructed as identical voltage dividers provided with a respective tapping for each further differential amplifier stage, PA1 the ratio of the instantaneous values of the control signals to one another is predetermined, and PA1 the division of the tappings of the voltage dividers and the ratio of the currents supplied by the reference current sources are adjusted to one another in such a manner that output signal components which exhibit a dependency on at least one higher power of the control signals cancel out.
on the one hand are coupled to one another and, via a first reference current source, to a first reference potential, and PA2 on the other hand are coupled to a respective output terminal as well as, via a respective output impedance, to a second reference potential, and whose control terminals can be supplied with a first control signal, an output signal being available at the output terminals, PA2 the main current paths of the further differential amplifier stages are connected to each time two pair-wise mutually symmetrical tappings, providing a predetermined division, of the two voltage dividers,
Circuit arrangements integrated on a semiconductor body often utilize differential amplifier stages which include amplifier members which are preferably formed by means of bipolar transistors. Inputs of such differential amplifier stages are then formed by base terminals of the bipolar transistors. Furthermore, the emitter terminals of the transistors are connected either directly, in which case they constitute a non-stabilized feedback differential amplifier, or they are linearized by resistance negative feedback. In the latter case the linearization resistors are connected to the emitter terminals of the transistors as emitter resistors and are connected in series with the main current paths of the amplifier members. The magnitude of the negative feedback is determined by the requirements imposed in respect of the noise factor, the linearity and the amplification of the differential amplifier stage. For example, the non-linear distortion factor or the magnitude of the so-called intermodulation products IPn, where n=2, 3, 4 . . . , is then taken as a measure of the linearity. These intermodulation products become manifest in the output signal of the differential amplifier stage as interference products and generally occur in the case of transmission of at least two signals of different frequency via a system having a non-linear transfer characteristic, being the differential amplifier stage in the present case, due to so-called cross-modulation. They may have a significant effect on the quality of the signal processed.
The article "A Linearization Technique for Variable Transconductors Using Emitter-Coupled Pairs and Its Application to a 1-Volt Active Filter", published in "Proceedings of ESCCIRC '90", pp. 165 to 168, discloses a circuit arrangement in which linearization of the characteristic of differential amplifier stages of the described kind is achieved by parallel operation of a plurality of individual differential amplifier stages. On the individual differential amplifier stages thereof appropriate input voltage shifts and weights of their "current tails" are imposed. Moreover, the emitter surface areas of the transistors used are chosen according to a predetermined ratio.
FIG. 1 shows a circuit arrangement which is constructed in this manner for the linearization of a non-stabilized feedback differential amplifier stage. In order to simplify the explanation, in comparison with the cited state of the art FIG. 1 shows the circuit arrangement with only two differential amplifier stages i.e. two emitter-coupled transistor pairs. The transistors denoted by the references Q1 and Q2 form a first differential amplifier stage and the transistors denoted by the references Q3 and Q4 form a second differential amplifier stage. The emitter surface areas of the transistors Q1 and Q4 are equal and a predetermined factor larger than the likewise mutually equal emitter surface areas of the transistors Q2 and Q3. The emitters of the transistors Q1, Q2 of the first differential amplifier stage are connected directly to one another and to ground via a first constant current source IO1. Analogously, the transistors Q3, Q4 of the second differential amplifier stage are connected directly to one another and to ground via a second constant current source IO2. The base terminals of the transistors Q1 and Q3 are connected to an input terminal in, the base terminals of the transistors Q2 and Q4 being connected to a second input terminal ini. The collector terminals of the transistors Q1, Q3 are connected together to an output terminal outi and, via a collector resistor R1, to a supply voltage terminal VCC. Analogously, a connection exists between the collector terminals of the transistors Q2, Q4 and a further output terminal out, via a second collector resistor R2 connected to the supply voltage terminal. As opposed to the circuit arrangement described in the cited article, the working impedances of the differential amplifier stages are constructed as resistors R1, R2; however, this does not change the basic operation of the circuit arrangement.
In the circuit arrangement shown in FIG. 1, the zero-crossing of the differential amplifier characteristic has been shifted to more negative input voltages in one of the differential amplifier stages and, to the same extent, to more positive input voltages in the other differential amplifier stage, so that as a result of addition of the two characteristics the differential output voltage is free from DC shifts (offset-free) and linearization of the superposed characteristics takes place. Compensation of the non-linear third-order component in the voltage at the output terminals out, outi is achieved notably for a surface ratio of 4:1 between the emitter surface areas of the transistors Q1, Q4 on the one side and Q2, Q3 on the other side.
Further linearization can be achieved by parallel connection of a plurality of such differential amplifier stages with appropriately selected surface area ratios.
However, it has been found that in the described circuit arrangement, for example, for a compensation of the non-linear third-order component with a surface area ratio of 4:1, the amplification of the overall circuit arrangement is reduced by 3.8 dB, corresponding to a factor of 1.55, in comparison with that of a simple differential amplifier stage. This reduction of the amplification is accompanied by a corresponding increase of the noise factor. Moreover, the relative spread of surface area ratios of emitter surfaces of bipolar transistors in integrated circuits is comparatively high, that is to say higher than, for example in the case of integrated resistors. This leads to manufacturing tolerances which are liable to degrade the achieved linearization.